Throughout this specification, including the claims:                a bus master is a type of interconnect master;        a bus target/slave is a type of an interconnect target;        a memory store coupled with a memory controller may be described at a higher level of abstraction as a memory store;        a peripheral may or may not have I/O pins;        a peripheral is connected to an interconnect that transports memory transfer requests;        a peripheral may be memory mapped, such that a memory transfer request to the interconnect target port of a peripheral is used to control that peripheral;        a processor core may be remotely connected to an interconnect over a bridge; and        a definition and description of domino timing effects can be found in [1].        
Many shared memory computing devices with multiple bus-masters/interconnect-masters, such as the European Space Agencies' Next Generation Microprocessor architecture [3] experience severe real-time problems [4]. For example, the memory transfer requests of software running on one core of the NGMP architecture experiences unwanted timing interference from unrelated memory transfer requests issued by other bus masters [4] over the shared ARM AMBA AHB [2] interconnect. For example, unwanted timing interference can occur by memory transfer requests issued by other cores and bus master peripherals to the level 2 cache module and SDRAM. Even though most memory transfer requests are in practice at most 32-bytes in length, a single memory transfer request can block the bus from servicing other memory transfer requests for more than 10 clock cycles.